Senior RTL Design Engineer
Education Requirements:
Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science
Experience Requirements:
8+ years of industry experience in RTL design, microarchitecture, and architecture development
Solid understanding of computer architecture fundamentals (pipelines, caches, coherence, memory hierarchies)
Hands-on experience with one or more subsystems: scheduling fabrics, high-performance interconnects, DMA engines, memory controllers, or datapath/control logic
Proficiency in Verilog/SystemVerilog and industry-standard RTL coding guidelines
Hands-on experience with simulation, synthesis, linting, and static timing analysis tools
Other Requirements:
Familiarity with timing constraints, physical design considerations, and EDA flows
Strong problem-solving and communication skills
Preferred: Network-on-chip (NoC), low-power design techniques, advanced technology nodes, emulation/FPGA prototyping, Python scripting
Responsibilities:
Design and implement RTL for Mythic's next-generation AI processor
Contribute to the development of a novel digital dataflow architecture, including a scheduling subsystem, high-performance interconnect fabric, and DMA engines
Develop and optimize high-performance, low-power components such as datapaths, controllers, memory subsystems, and interconnects
Collaborate with architects and verification engineers to define microarchitecture and ensure functional correctness
Drive timing closure by working closely with synthesis and physical design teams
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