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Alternative Military Service Program
Optimize edge AI performance with ultra-low power consumption and GPU-level accuracy using award-winning NPU chips and modules for smart industrial applications.
Benefits:
Stock options equivalent to annual salary for all full-time employees
Latest high-spec laptops and standing desks
Support for breakfast, lunch, and dinner
Unlimited snacks, ice cream, and drinks in the office cafe
Fitness center and sauna membership support
Experience Requirements:
Experience not required
Other Requirements:
Candidates with less than 3 years of experience are required to submit their academic transcripts
If any false information is found in application documents, the job offer may be withdrawn
Responsibilities:
Develop ROM boot code and bootloaders
Design and implement a real-time inference engine
Analyze state-of-the-art (SOTA) generative AI models
Develop deep learning compilers optimized for products
Design RTL-based hardware IPs related to AI processor architecture
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Physical Design Engineer
Optimize edge AI performance with ultra-low power consumption and GPU-level accuracy using award-winning NPU chips and modules for smart industrial applications.
Benefits:
Stock options equivalent to annual salary for all full-time employees
Latest high-spec laptops and standing desks
Support for breakfast, lunch, and dinner
Unlimited snacks, ice cream, and drinks in the office cafe
Fitness center and sauna membership support
Education Requirements:
Bachelor’s degree or higher in Electrical/Electronic Engineering or related field
Experience Requirements:
Minimum 5 years of experience
Experience or project work in ASIC physical design
Hands-on experience with major EDA tools (ICC2, Innovus)
Proficiency in scripting languages (Tcl, Perl, Python)
Responsibilities:
Perform full physical design implementation for NPU chips
Synthesis, floorplanning, placement, clock tree synthesis (CTS), and routing
Timing closure and optimization of power, area, and performance (PPA)
Post-layout verification and debug: DRC, LVS, Crosstalk, EMIR
Automate physical design flows using scripting
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System SoC SW Test Engineer
Optimize edge AI performance with ultra-low power consumption and GPU-level accuracy using award-winning NPU chips and modules for smart industrial applications.
Benefits:
Stock options equivalent to annual salary for all full-time employees
Latest high-spec laptops and standing desks
Support for breakfast, lunch, and dinner
Unlimited snacks, ice cream, and drinks in the office cafe
Fitness center and sauna membership support
Education Requirements:
Bachelor’s degree or higher in Computer Science, Electrical Engineering, or related field
Experience Requirements:
Minimum 5 years of experience
Experience in software testing and quality assurance (QA)
Proficiency in Python, C/C++
Development and debugging experience in Linux environments
Responsibilities:
Perform functional and performance testing on NPU software stack
Design test plans and test cases and build automated test environments
Report, reproduce, and analyze bugs and propose improvements
Ensure software quality and continuous testing in CI/CD environments
Validate performance and compatibility based on application scenarios
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SoC Physical Design Engineer
Optimize edge AI performance with ultra-low power consumption and GPU-level accuracy using award-winning NPU chips and modules for smart industrial applications.
Benefits:
Stock options equivalent to annual salary for all full-time employees
Latest high-spec laptops and standing desks
Support for breakfast, lunch, and dinner
Unlimited snacks, ice cream, and drinks in the office cafe
Fitness center and sauna membership support
Education Requirements:
Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field
Experience Requirements:
10+ years of experience in ASIC Physical Design
Proficiency with EDA tools such as Synopsys or Cadence
Understanding of STA and Low Power Design Methodologies
In-depth knowledge of DFM rules
Responsibilities:
Perform RTL-to-GDSII Physical Design (Synthesis, Place & Route, Timing Closure)
Conduct low-power design and power optimization
Run physical verification (DRC, LVS, ERC) and signal integrity checks
Optimize PPA (Power, Performance, Area)
Develop and automate Physical Design flows for advanced technologies
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DDR Memory Subsystem SoC Engineer
Optimize edge AI performance with ultra-low power consumption and GPU-level accuracy using award-winning NPU chips and modules for smart industrial applications.
Benefits:
Stock options equivalent to annual salary for all full-time employees
Latest high-spec laptops and standing desks
Support for breakfast, lunch, and dinner
Unlimited snacks, ice cream, and drinks in the office cafe
Fitness center and sauna membership support
Education Requirements:
Bachelor's degree or higher in Electrical/Computer Engineering or a related field
Experience Requirements:
Minimum 3 years of experience
Deep understanding of JEDEC DDR/LPDDR standards (DDR4/5, LPDDR4/5, etc.)
Proficiency in scripting languages such as Python, Perl, and Tcl
Responsibilities:
3rd-Party DDR IP Integration and SoC Interface Verification
Perform functional and performance verification regressions of the DDR subsystem
Collaborate with firmware teams for DDR initialization and training
Lead DDR interface bring-up and stability verification on actual boards
Develop test patterns for mass production ATE test environments
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Overseas Sales (China Market)
Optimize edge AI performance with ultra-low power consumption and GPU-level accuracy using award-winning NPU chips and modules for smart industrial applications.
Benefits:
Stock options equivalent to annual salary for all full-time employees
Latest high-spec laptops and standing desks
Support for breakfast, lunch, and dinner
Unlimited snacks, ice cream, and drinks in the office cafe
Fitness center and sauna membership support
Education Requirements:
Bachelor’s degree or higher
Experience Requirements:
Minimum 3 years of experience in overseas or B2B sales
Other Requirements:
Strong communication skills in Chinese and Korean
Eligible for international travel without restrictions
Responsibilities:
Drive sales of semiconductor (NPU) products and solutions in the Chinese market
Identify new customers and manage relationships with existing clients
Manage local partners and distributors in China
Conduct market and competitor analysis and establish sales strategies
Collaborate with the product/technical team to deliver tailored proposals
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PCIE Link (Controller) Design Engineer
Optimize edge AI performance with ultra-low power consumption and GPU-level accuracy using award-winning NPU chips and modules for smart industrial applications.
Benefits:
Stock options equivalent to annual salary for all full-time employees
Latest high-spec laptops and standing desks
Support for breakfast, lunch, and dinner
Unlimited snacks, ice cream, and drinks in the office cafe
Fitness center and sauna membership support
Education Requirements:
Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field
Experience Requirements:
Minimum 3 years of experience
Strong understanding of PCIe protocol (Gen4/Gen5)
Proficiency in RTL design using Verilog/SystemVerilog
Experience in synthesis, timing analysis, and FPGA prototyping
Responsibilities:
Design and implementation of PCIe Controller and Link Layer logic for NPU SoCs
Integration and verification of PCIe IP in RTL design
Development of PCIe protocol logic including configuration and flow control
Performance optimization and validation of PCIe interfaces
Collaboration with verification, firmware, and system teams
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PCB Module Manufacturing & Production Engineer (10+ Years Experience)
Optimize edge AI performance with ultra-low power consumption and GPU-level accuracy using award-winning NPU chips and modules for smart industrial applications.
Benefits:
Stock options equivalent to annual salary for all full-time employees
Latest high-spec laptops and standing desks
Support for breakfast, lunch, and dinner
Unlimited snacks, ice cream, and drinks in the office cafe
Fitness center and sauna membership support
Experience Requirements:
10+ years of experience in production engineering (PE)
Deep understanding and hands-on experience in SMT processes and PCB module assembly
Other Requirements:
No disqualifying factors for frequent business trips and on-site duties at global production bases
Responsibilities:
Technical Management of Outsourced Production Lines (EMS)
Analyze causes of defects and implement yield improvement measures
Manage the transfer of new products to mass production
Conduct regular factory visits and due diligence to inspect component suitability
Manage product development and production processes in accordance with ISO 9001
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Android Framework Development Engineer
Optimize edge AI performance with ultra-low power consumption and GPU-level accuracy using award-winning NPU chips and modules for smart industrial applications.
Benefits:
Stock options equivalent to annual salary for all full-time employees
Latest high-spec laptops and standing desks
Support for breakfast, lunch, and dinner
Unlimited snacks, ice cream, and drinks in the office cafe
Fitness center and sauna membership support
Experience Requirements:
Minimum 3 years of experience
Deep understanding of Android Internals (AOSP)
Experience in Linux-based system programming
Other Requirements:
Strong C++ proficiency
Must be able to pass a rigorous coding test using C++
Responsibilities:
Integrate DEEPX NPU Runtime (RT) libraries into the Android Framework
Develop and modify the lower layers of the Android stack (HAL, Native Daemons)
Implement and optimize the data path between Android Application layer and NPU
Ensure communication between Android NNAPI and DEEPX driver
Trace and resolve complex system-level issues across Hardware, Kernel, and Android layers
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Culture Planner
Optimize edge AI performance with ultra-low power consumption and GPU-level accuracy using award-winning NPU chips and modules for smart industrial applications.
Benefits:
Stock options equivalent to annual salary for all full-time employees
Latest high-spec laptops and standing desks
Support for breakfast, lunch, and dinner
Unlimited snacks, ice cream, and drinks in the office cafe
Fitness center and sauna membership support
Experience Requirements:
10 years+ in HR/People Ops
Ideally within a high-growth tech startup or a fast-paced semiconductor/AI environment
Proven experience in environments that demand exceptional levels of dedication
Other Requirements:
Fluent in Korean and English
Bilingual communication skills
Responsibilities:
Lead the design and implementation of DEEPX’s unique organizational culture
Translate the company’s core philosophy into high-impact cultural rituals
Foster a culture where results are the primary measure of success
Ensure all internal communications reflect a high-performance mindset
Design initiatives that safeguard the team’s grit through results
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Manufacturing Application Engineer
Deliver petascale-class AI inference with 50% less power consumption than leading GPUs using purpose-built chiplet hardware for hyperscale data center workloads.
Experience Requirements:
Experience shipping reliable software in real-world environments
Other Requirements:
Proficiency in Python (Async, IO) and TypeScript/JavaScript (Next.js/React)
Practical understanding of peripheral/device control and drivers
Solid understanding of networking fundamentals and Linux system debugging
Responsibilities:
Design and operate production-grade apps for HW screening and factory workflows
Build Python-based backends for device control, log parsing, and automated validation
Develop Next.js Web UIs for monitoring, error triage, and configuration management
Implement peripheral control and integration (USB, UART, I2C, SPI) with a focus on safety
Troubleshoot full-stack issues from device connectivity to system-level latency
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IR Manager
Deliver petascale-class AI inference with 50% less power consumption than leading GPUs using purpose-built chiplet hardware for hyperscale data center workloads.
Experience Requirements:
5+ years of relevant experience, with 3+ years in disclosure for listed companies
Other Requirements:
Experience performing disclosure duties with FSS/KRX
High understanding of the Commercial Act, Capital Markets Act, and exchange disclosure regulations
Responsibilities:
Support preparation of listing documents and materials for IPO readiness
Management of disclosure schedules and preparation of periodic/occasional disclosure materials
Response to regulatory agencies and monitoring of major laws and regulations
Planning and operation support for IR activities targeting domestic and international shareholders
Support for shareholder communication tasks
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Partner Operations Manager
Deliver petascale-class AI inference with 50% less power consumption than leading GPUs using purpose-built chiplet hardware for hyperscale data center workloads.
Experience Requirements:
5+ years of B2B partnership, channel management, or alliance related experience
Other Requirements:
Understanding of IT, semiconductor, cloud, AI, or data center industries
Basic business understanding of partner contracts, collaboration structures, and revenue models
Basic understanding of server hardware components and manufacturing processes
Business-level English communication skills
Responsibilities:
Lifecycle management from partner onboarding to enablement programs and performance management
Management of partner sales pipeline and business performance analysis
Execution of GTM strategy through collaboration with partner organizations
Establishment of purchase strategies for AI servers and hardware components
Cost optimization and establishment of supply systems with server production partners
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Finance Manager
Deliver petascale-class AI inference with 50% less power consumption than leading GPUs using purpose-built chiplet hardware for hyperscale data center workloads.
Experience Requirements:
3+ years of experience in finance and accounting
Practical experience in accounting and settlement
Other Requirements:
Experience in reporting and paying national/local taxes like VAT and corporate tax
Experience using Douzone ERP
Responsibilities:
Monthly closing and preparation of financial statements
Reviewing the completeness of sales/purchase tax invoices
Settlement of corporate cards and management of unresolved items
Preparation of account specifications based on settlement
Responding to external audits and investor requests
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Experience Marketing Coordinator
Deliver petascale-class AI inference with 50% less power consumption than leading GPUs using purpose-built chiplet hardware for hyperscale data center workloads.
Experience Requirements:
1-3 years of digital marketing or content-related experience
Other Requirements:
Excellent document writing and editing skills
Smooth communication and collaboration skills
Strong execution ability to manage multiple tasks and meet deadlines
Responsibilities:
Content management and updates for the company website and related platforms
Support marketing for domestic and international events
Production and localization of marketing materials such as presentations and SNS content
Collaborate with design, product, engineering, and business teams
Operational support for communication and branding activities
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Framework Software Engineer
Deliver petascale-class AI inference with 50% less power consumption than leading GPUs using purpose-built chiplet hardware for hyperscale data center workloads.
Education Requirements:
Master's or higher degree in Computer Science, Electrical Engineering, or a related field
Experience Requirements:
Strong experience with Python, C++ and PyTorch, including model execution and runtime internals
Hands-on experience with inference serving or high-performance ML systems
Other Requirements:
Familiarity with Linux systems, profiling tools, and debugging performance bottlenecks
Strong problem-solving skills and the ability to reason about system-level trade-offs
Clear communication skills and ability to collaborate in a fast-paced environment
Responsibilities:
Design, develop, and optimize high-performance inference frameworks for large-scale distributed serving
Improve end-to-end serving performance (TTFT, ITL, throughput, tail latency)
Design scalable multi-node serving architectures
Analyze and optimize memory usage, device utilization, and communication overhead
Build and maintain benchmarks and simulators for AI serving workloads
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Legal Counsel
Deliver petascale-class AI inference with 50% less power consumption than leading GPUs using purpose-built chiplet hardware for hyperscale data center workloads.
Experience Requirements:
Experience of 4 to 10 years in a law firm or corporate legal team
Other Requirements:
Domestic (Korean) attorney license holder
Experience in business English communication preferred
Responsibilities:
Establishment and inspection of compliance control standards under the Commercial Act
Review, drafting, and modification of Korean/English contracts
Legal risk review and negotiation support
Response to domestic and international litigation/disputes
Establishment and operation support of compliance systems at the level of listed companies
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Ethernet Firmware Engineer
Deliver petascale-class AI inference with 50% less power consumption than leading GPUs using purpose-built chiplet hardware for hyperscale data center workloads.
Education Requirements:
Bachelor’s or higher degree in Electrical Engineering or Computer Engineering
Experience Requirements:
Minimum of 5 years of experience in next-generation Ethernet firmware development
Other Requirements:
Deep understanding of Ethernet protocols (Layer 2/3, TCP/IP, UDP)
Strong background in silicon validation, embedded software development, and proven debugging skills
Excellent communication and problem-solving abilities
Responsibilities:
Evaluate and develop Ethernet control subsystem firmware
Optimize and implement Layer 2/3 protocols
Implement and debug RoCE (RDMA) functionality
Integrate hardware and software architectures to evaluate systems
Provide solutions for technical issues and ensure system performance
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PCIe Firmware Engineer
Deliver petascale-class AI inference with 50% less power consumption than leading GPUs using purpose-built chiplet hardware for hyperscale data center workloads.
Education Requirements:
Bachelor’s or higher degree in Electrical Engineering, Computer Engineering
Experience Requirements:
Minimum of 5 years of experience in hardware-software integration, validation, driver/firmware development, and testing on PCIe(Gen3/4/5)
Other Requirements:
Deep understanding of PCIe protocol(Gen3/4/5)
Strong background in silicon validation and embedded software development, proven debug skills
Excellent communication and problem-solving skills
Responsibilities:
PCIe subsystem control firmware development
LTSSM and power state management
DMA, ATU, ATS, SRIOV and customized features implementation
PCIe sub system integrated programmable core firmware development
Support and debug PCIe compliance tests
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