Staff Engineer - CPU & ISA Architecture (Europe based)
Benefits:
pension plan
extensive employee insurances
option to get company shares
Education Requirements:
MS/PhD in CE/EE/CS
Experience Requirements:
expertise in CPU design, analysis, and modeling
Other Requirements:
RISC-V
ARM
gem5
Verilog
SystemVerilog
Responsibilities:
Research, design, and evaluate CPU microarchitectural components
Build and validate performance/functional models
Develop architectural extensions within RISC-V
Propose and prototype new mechanisms for efficiency
Work with hardware, compiler, and system teams
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