In a significant move poised to shape the future of artificial intelligence and high-performance computing, electronic design automation (EDA) leader Cadence Design Systems has deepened its long-standing collaboration with foundry giant Taiwan Semiconductor Manufacturing Co. (TSMC). The partnership is centered on accelerating the development of next-generation chips by optimizing Cadence's AI-driven design software and intellectual property (IP) for TSMC's most advanced and forthcoming manufacturing processes.[1][2][3] This collaboration equips chip designers with the tools necessary to tackle the immense complexity of creating the powerful, efficient processors required for demanding AI workloads, from large-scale data centers to emerging AI-powered personal computers.[4] The joint effort spans the entire design ecosystem, encompassing AI-powered EDA flows, sophisticated 3D-IC packaging solutions, and a portfolio of silicon-proven IP, all tailored for TSMC's cutting-edge N2, A16, and N3P process nodes.[5][6][3]

A central pillar of the expanded partnership is the certification and optimization of Cadence's digital and custom design flows for TSMC’s next wave of semiconductor technologies. Cadence's AI-powered design suites now support TSMC's 2-nanometer (N2) and angstrom-era A16 processes, a critical step that enables mutual customers to begin designing the chips of tomorrow.[5][7] The N2 process, slated for volume production in 2025, represents a major architectural shift as TSMC's first technology to utilize gate-all-around (GAA) nanosheet transistors, promising substantial improvements in performance and energy efficiency over its 3nm predecessors.[8][9][10] Looking further ahead, the A16 process, expected by 2026, will integrate these advanced nanosheet transistors with an innovative backside power delivery network called Super Power Rail, a design intended to boost performance by 8-10% and reduce power consumption by 15-20% compared to the N2P node, specifically targeting the needs of HPC and AI accelerators.[11][12] Cadence's AI-driven tools, including the Cerebrus Intelligent Chip Explorer and the JedAI Platform, have been validated by TSMC to help designers achieve optimal power, performance, and area (PPA) on these advanced nodes and even automate complex tasks like fixing design rule violations, thereby speeding up design closure.[6][13][4]

Beyond the raw processing nodes, the collaboration delivers a crucial component for modern chip design: readily available, pre-verified intellectual property. Cadence has announced a suite of new silicon-proven IP for TSMC's N3P process, an enhanced version of its 3nm technology. This portfolio directly addresses the bottlenecks that currently constrain AI systems, particularly memory and data transfer speeds.[2] Key offerings include the industry's first HBM4 high-bandwidth memory IP and advanced LPDDR6/5x interfaces, designed to feed data-hungry AI processors more efficiently.[5][2] Furthermore, the availability of cutting-edge connectivity IP, such as PCI Express (PCIe) 7.0 and the Universal Chiplet Interconnect Express (UCIe) 32G, is vital for enabling the next generation of server infrastructure and the burgeoning chiplet ecosystem, where processors are constructed from smaller, specialized dies.[2][4] By providing these pre-verified IP blocks, Cadence and TSMC significantly lower the barrier to entry for designing complex SoCs, reducing development time and risk for their customers.

The partnership also extends into the third dimension, tackling the growing importance of advanced packaging. As traditional monolithic chip scaling slows, 3D-IC technology, which involves stacking multiple chips or chiplets vertically, has become essential for continuing performance gains.[14] The collaboration enhances Cadence's 3D-IC solutions to fully support TSMC's 3DFabric packaging technologies.[5][15] This integration provides designers with automated tools for managing the intricate connections between stacked dies, optimizing the placement of chiplets, and conducting critical thermal and power integrity analyses across the entire 3D stack.[14][4] This holistic approach, which combines advanced silicon processes with sophisticated packaging techniques, is fundamental to building the highly integrated, high-bandwidth systems required for the AI era, effectively allowing designers to create a single, powerful system from multiple interconnected components.[14]

Ultimately, the strengthened alliance between Cadence and TSMC represents a foundational enabler for the entire semiconductor industry as it navigates the escalating demands of the AI revolution. By co-optimizing design software, manufacturing processes, and IP, the two companies are creating a more streamlined and efficient path from chip architecture to high-volume production.[2][13] This synergy allows chip developers to fully leverage the power and efficiency of TSMC's next-generation nodes while managing the inherent design complexity with Cadence's intelligent, AI-powered tools. As the industry pushes toward angstrom-scale silicon and complex multi-chiplet systems, collaborations of this depth are no longer just beneficial but essential for driving the innovation that will power future advancements in everything from hyperscale computing and mobile communications to automotive and life sciences.[1] The work even extends to TSMC's future A14 process, indicating a long-term commitment to preparing the design ecosystem well ahead of manufacturing readiness.[5][6]