Lightmatter
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About
Lightmatter is a pioneer in photonic computing, designing hardware that uses light instead of electricity to move and process data. The company's primary focus is on overcoming the "interconnect bottleneck" in AI data centers, where traditional electrical wiring and copper-based systems can no longer keep up with the massive data demands of large-scale AI model training. By leveraging silicon photonics, Lightmatter provides high-speed, energy-efficient communication between GPUs, TPUs, and other specialized processors, enabling next-generation AI infrastructure to scale beyond current physical limits. The platform revolves around its Passage technology, which includes 3D Co-Packaged Optics (CPO). This hardware features an industry-first "Edgeless I/O" architecture that vertically stacks an Electronic Integrated Circuit (EIC) directly with a Photonic Integrated Circuit (PIC) within a single chiplet. This design allows for significantly higher bandwidth density and lower power consumption compared to conventional lateral interconnects. Key products include the L-Series for standards-compliant scaling and the M1000 Superchip, which is specifically designed to provide massive scale-up bandwidth and radix for the world's largest training clusters. Lightmatter's solutions are built for hyperscale data center operators, semiconductor manufacturers, and hardware engineers who need to scale AI compute performance for decades to come. It is particularly relevant for industries focused on massive-scale AI training, high-performance computing (HPC), and cloud infrastructure. Unlike traditional networking solutions that rely on external optical transceivers, Lightmatter integrates optics directly into the chip package, which drastically reduces latency and energy waste while increasing the total available bandwidth per package. What distinguishes Lightmatter from other semiconductor companies is its heavy emphasis on deployability and standardization. The company offers proprietary Detachable Fiber Technology for easier field serviceability and wafer-level passive alignment during manufacturing, which improves yields. Furthermore, its products support a wide spectrum of lane speeds from 56G NRZ to 448G PAM4 across up to 16 wavelengths. By actively participating in standards bodies like the Open Compute Project and UALink, Lightmatter ensures its photonic solutions can be integrated into the evolving global hardware ecosystem.
Pros & Cons
Achieves an 8X leap in bidirectional fiber bandwidth density.
Supports high-volume scalability with wafer-level passive alignment.
Vertical chip stacking significantly reduces power consumption and physical footprint.
Detachable fiber design simplifies field serviceability and maintenance in data centers.
Compatible with a wide range of lane speeds from 56G to 448G.
Requires complex hardware integration rather than simple software implementation.
Primarily designed for hyperscale data centers, making it inaccessible for small-scale users.
Use Cases
Data center infrastructure engineers can use the Passage L-Series to scale optical interconnects while maintaining compliance with standard packaging.
Hardware manufacturers can implement Near-Packaged Optics to add high-bandwidth connectivity to existing PCBs without modifying the core chip package.
AI model developers can utilize the M1000 Reference System to achieve the bandwidth necessary for massive-scale training clusters.
Platform
Features
• rack-scale validation system
• near-packaged optics (npo) support
• detachable fiber technology
• l-series linear drive cpo
• passage m1000 superchip
• 16-wavelength bidirectional links
• edgeless i/o architecture
• 3d co-packaged optics (cpo)
FAQs
What is Lightmatter's Passage technology?
Passage is a 3D co-packaged optics platform that integrates photonic and electronic circuits to enable high-bandwidth, low-power data movement. It is designed to connect XPUs and switches at speeds that traditional copper interconnects cannot achieve.
What speeds do Lightmatter interconnects support?
The platform is highly scalable, supporting lane speeds ranging from 56G NRZ to 448G PAM4. It also supports both bidirectional and unidirectional links with up to 16 different wavelengths.
How does the Detachable Fiber Technology work?
This technology uses wafer-level passive alignment to ensure placement accuracy without V-grooves. It allows for simple fiber maintenance and replacement in data centers, ensuring higher uptime for mission-critical workloads.
What is Edgeless I/O architecture?
Edgeless I/O is a design where the electronic and photonic circuits are stacked vertically rather than horizontally. This removes the limitations of chip-edge spacing, allowing for much denser and more efficient data input/output.
Pricing Plans
Enterprise
Unknown Price• Passage L-Series CPO access
• Passage M1000 Reference System
• Edgeless I/O technology
• Detachable Fiber Technology
• Rack-scale validation
• Custom wavelength configurations
• Hardware deployment support
• Integration with standard packaging flows
Job Opportunities
Analog Design, Intern
Scale AI data center performance with high-bandwidth photonic interconnects that eliminate traditional copper bottlenecks for hyperscale infrastructure teams.
Benefits:
Comprehensive Health Care Plan
Retirement Savings Matching Program
Life Insurance
Generous Time Off
Paid Family Leave
Education Requirements:
Enrolled in a graduate engineering program
ECE, EE or Computer Engineering degree
Experience Requirements:
Interest in Analog/Mixed-signal IC design
Exposure/Understanding of CMOS device characteristics
Exposure to designing analog blocks
Other Requirements:
Export Control compliance
Responsibilities:
Learn the Analog Design Flow
Learn industry standards using Cadence Virtuoso
Participate in the design of highly integrated photonics chip
Run post-layout and mixed-signal top-level simulations
Validate performances of the circuits in the lab
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Analog IC Design Engineer, AMS
Scale AI data center performance with high-bandwidth photonic interconnects that eliminate traditional copper bottlenecks for hyperscale infrastructure teams.
Benefits:
Comprehensive Health Care Plan
Retirement Savings Matching Program
Life Insurance
Generous Time Off
Paid Family Leave
Education Requirements:
MS with 8+ years experience
Ph.D. with 5+ years experience
Experience Requirements:
Designing analog and mixed-signal circuits
Understanding of CMOS device characteristics
Experience with Cadence Design Environment
Experience testing analog circuits in a lab environment
Other Requirements:
Export Control compliance
Responsibilities:
Design analog/mixed-signal (AMS) circuits
Support micro-architecture development
Collaborate with design engineering teams
Document design simulations
Drive block-level floorplan
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Analog IC Design Engineer, High-Speed
Scale AI data center performance with high-bandwidth photonic interconnects that eliminate traditional copper bottlenecks for hyperscale infrastructure teams.
Benefits:
Comprehensive Health Care Plan
Retirement Savings Matching Program
Life Insurance
Generous Time Off
Paid Family Leave
Education Requirements:
MS with 6+ years experience
Ph.D. with 3+ years experience
Experience Requirements:
GHz-speed RF or broadband analog design
Experience with Tx/Rx equalization techniques
Familiarity with SERDES architectures
Experience with Cadence Design Environment
Other Requirements:
Export Control compliance
Responsibilities:
Support micro-architecture development
Collaborate with design engineering teams
Design analog/mixed-signal blocks
Document design simulations
Drive block-level floorplan
Show more details
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