Cerebras Systems

Education Requirements:

• BS or MS in Electrical Engineering or equivalent

Experience Requirements:

• 10+ years of circuit design and analysis experience

Other Requirements:

• Strong knowledge of leading edge CMOS FinFet technology and transistor behavior

• Expert at running circuit level simulations across a variety of design types

• Expert with Hspice and Finesim type simulation tools

• Good understanding of techniques for optimizing clock distribution

• Good understanding of power supply distribution, IR drop problems and how to analyze them

• Experience running aging simulations & knowledge of NBTI ,PBTI, HCI

• Good understanding of IO circuits, ESD circuits and their analysis

• Experience with analyzing power dissipation and making recommendations for optimizations

• Strong ability in scripting languages like Tcl and Python

• Demonstrated ability to work with cross functionally to resolve problems

• Excellent analytical, and problem-solving skills

• Strong interpersonal skills and a willingness to collaborate effectively are essential qualities for success in any team

• Extremely self-motivated and eager to solve problems

Responsibilities:

• circuit design tasks including clock design, power simulations, IO design, ESD, aging simulations, memory evaluations, datapath, and standard cell customizations

• design and analyze custom circuits

• circuit analysis of our wafer scale engine

Education Requirements:

• BS or MS in Computer Science or Electrical Engineering

Experience Requirements:

• 5 years of Design Verification experience

Other Requirements:

• Great debugging and problem-solving skills

• Deep knowledge of SystemVerilog testbench language, DPI and UVM

• Excellent programming skills and knowledge of software engineering practices including object-oriented design

• Experience developing scalable and portable testbenches and components

• Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations

• Proficient in a scripting language such as Python or Perl

• Good interpersonal skills and ability & desire to work as a standout colleague are a must

• Extremely self-motivated and eager to solve problems

Responsibilities:

• Work with RTL designers and software engineers to ensure a high-quality design that works first silicon

• Develop detailed test and coverage plans based on the micro-architecture

• Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage

• Write tests, manage regressions, gather coverage, and debug test failures

Education Requirements:

• BS or MS in Electrical Engineering, Computer Science or similar

Experience Requirements:

• 10+ years of flow development and or scripting for physical design

Other Requirements:

• Expert at generating structured placement and routing

• Expert at characterization automation

• Expert in scripting languages like Tcl and Python. Ability to develop PD flows, tools and augmentation scripts

• Experience with the complete physical design flow. Knowledge of Synopsys tool suite is a plus.

• Good understanding of full chip floorplanning and integration.

• Good knowledge of server infrastructure and experience with integrating AWS and internal compute resources

• Demonstrated ability to work with RTL teams to optimize for physical design

• Excellent analytical, and problem-solving skills

• Good interpersonal skills and ability & desire to work as a standout colleague are a must.

• Extremely self-motivated and eager to solve problems

Responsibilities:

• Physical Design automation

• projects involving scripted placement, routing, library cell characterization, and providing support for server infrastructure